1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device suitable for use as a floating-body cell (will be referred to as “FBC” hereunder) type semiconductor memory having a charge-storage region.
2. Background Art
In the field of semiconductor memories, there has been used the 1T-1C (one transistor/one capacitor) type DRAM. Currently, however, it appears that the cell size cannot further be reduced, and therefore a semiconductor memory having a new structure has been sought. A semiconductor device having a data storage region formed under a transistor itself has been proposed as one of the typical examples of such a new-structure semiconductor memory thus sought.
The FBC memory is known as such a semiconductor device. It was introduced during a lecture given in the ISSCC 2002 (International Solid-State Circuit Conference 2002, held in San Francisco, Mar. 3–7, 2002). The details of this memory were clarified in “ISSCC 2002/SESSION 9/DRAM AND FERROELECTRIC MEMORIES /9.1/Memory Design Using One-Transistor Gain Cell on SOI/Takashi Ohsawa et al.” An FBC memory made experimentally under the 0.175-μm rule was reported as an example.
The above FBC cell includes an MOS transistor formed on an SOI (silicon on insulator) substrate. It has no separate charge-storage capacitor but a charge-storage region formed under the transistor.
Since the semiconductor device having the above structure needs no separate capacitor, it can easily be miniaturized, integrated to a higher degree, and have the speed of operation enhanced.
Note that generally, the demand for mounting the semiconductor device along with a higher-speed logic LSI in one chip has been larger and larger and also a higher consistency of the logic LSI with the manufacturing process has also been demanded for a simpler process.
FIGS. 22 to 25 show together an FBC memory as a typical example of the conventional semiconductor devices known to the Inventors of the present invention. FIG. 22 is a plan view, FIG. 23 shows sectional views of the conventional semiconductor device, taken along lines B—B and C—C, respectively, in FIG. 22, FIG. 24 shows sectional views taken along lines D—D and E—E, respectively, FIG. 22, and FIG. 25 is a plan view corresponding to FIG. 22. FIG. 25 shows a physical relationship between strip-shaped element isolation films 8 and, silicon layers 4 sandwiched between the isolation films 8 and diffusion layers 6S and 6D formed as source/drain layers on the silicon layers 4, among others.
As especially shown in FIG. 23(B), the above conventional semiconductor device is formed on an SOI substrate 100. The SOI substrate 100 is a lamination of a support substrate (p-type semiconductor substrate) 1, n-type diffusion layer 2, embedded oxide film (SiO2) 3 and a p-type silicon layer 4.
As especially shown in FIGS. 24(D) and 24(E) and 25, the uppermost silicon layer 4 has the element isolation films 8 formed thereon. As especially shown in FIG. 25, the element isolation films 8 is strip-shaped and extend horizontally in the plane of the drawing. As also shown in FIG. 23(C), these element isolation films 8 extend horizontally (in the plane of the drawing) below and between bit lines BL that will be described in detail later. As shown in FIG. 25, ones of the silicon layers 4, located between the element isolation layers 8, are so-called strip-shaped element regions 4a. The strip-shaped element regions 4aoverlap the bit lines BL vertically and extend under, and in the same direction as, the bit lines BL in the plane of FIG. 22(A). Each of the strip-shaped element regions 4ahas N+ diffusion layers 6D and 6S formed thereon at predetermined intervals as especially shown in FIGS. 23(B) and 25. In the case of one of these element regions 4a, for example, the element region 4a(j), parts thereof sandwiched between the diffusion layers 6D and 6S provide the silicon regions 4b in which channels are to be formed. Further, of the diffusion layers 6S and 6D, the diffusion layer 6S forms a source and the diffusion layer 6D forms a drain. They are alternately arranged as shown. As shown in FIG. 23(B), hot holes developed when a current flows from the drain (diffusion layer 6D) to the source (diffusion source 6S) via the silicon region 4b where the channel is to be formed are stored in the silicon region 4b. Gate electrodes 7 are formed on the silicon regions 4b with gate oxide layers 6 being laid between them. As shown in FIG. 22(A), the gate electrodes 7 are strip-shaped and extend vertically in the plane of the drawing. Also, on the diffusion layers 6S, there are formed source line SL each of which is a lamination of a strip-shaped contact plug 9S and a strip-shaped metal layer 10S. The contact plug 9S and metal layer 10S extend vertically in the plane of FIG. 22(A). Also, the diffusion layer 6D have each bit line BL extending horizontally as in FIG. 22(A) connected thereto via columnar contact plugs 9D as contacts. Note that the reference 11 indicates an interlayer insulating layer.
As seen from the above and as especially shown in FIG. 25, the silicon layers 4 are sandwiched between the element isolation films 8 to have a strip-like shape and extend horizontally in the plane of the drawing and the cells adjacent to each other in the plane of the drawing are isolated from each other by the N+ diffusion layers 6S and 6D being a source/drain, respectively.
However, in case the memory cell is miniaturized to such a high degree that the bit line of the N+ diffusion layer 7 is as short as 0.1 μm or so in the 0.1-μm generation, for example, the bipolar operation among P, N+ and P taking place among the adjacent cells in FIG. 23(B) is not negligible and data stored in the cells will be damaged due to their mutual interference in the worst case.
The above problem will be solved by raising the impurity concentration in the N+ diffusion layers 6S and 6D being a source/drain, respectively. In the case of the FBC structure, however, such a raised impurity concentration will increase the junction leakage between a floating body as a memory region and the source/drain, resulting in a considerably low data storage function.
As above, the conventional semiconductor device has such a problem that a higher integration results in an insufficient isolation between elements and increasing the impurity concentration in the diffusion layers forming a source and drain, respectively, to improve the inter-cell isolation results in the junction leakage current and also in a deteriorated storage capability of the floating body.